Harry Wagstaff

Orcid: 0000-0002-2079-8596

According to our database1, Harry Wagstaff authored at least 16 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2019
Mitigating JIT compilation latency in virtual execution environments.
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019

Full-System Simulation of Mobile CPU/GPU Platforms.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018
A Retargetable System-level DBT Hypervisor.
ACM Trans. Comput. Syst., 2018

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.
Proc. IEEE, 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018

Algorithmic Performance-Accuracy Trade-off in 3D Vision Applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

2017
SimBench: A portable benchmarking methodology for full-system simulators.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016
Hardware-Accelerated Cross-Architecture Full-System Virtualization.
ACM Trans. Archit. Code Optim., 2016

Efficient asynchronous interrupt handling in a full-system instruction set simulator.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
From high level architecture descriptions to fast instruction set simulators.
PhD thesis, 2015

Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2014
Efficient code generation in a region-based dynamic binary translator.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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