Björn Franke

According to our database1, Björn Franke authored at least 62 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Mitigating JIT compilation latency in virtual execution environments.
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019

A Retargetable System-Level DBT Hypervisor.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Full-System Simulation of Mobile CPU/GPU Platforms.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Low-cost deterministic C++ exceptions for embedded systems.
Proceedings of the 28th International Conference on Compiler Construction, 2019

2018
Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.
Proceedings of the IEEE, 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018

Right-Sizing Server Capacity Headroom for Global Online Services.
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

Generalized profile-guided iterator recognition.
Proceedings of the 27th International Conference on Compiler Construction, 2018

Towards a compiler analysis for parallel algorithmic skeletons.
Proceedings of the 27th International Conference on Compiler Construction, 2018

2017
Free Rider: A Source-Level Transformation Tool for Retargeting Platform-Specific Intrinsic Functions.
ACM Trans. Embedded Comput. Syst., 2017

SimBench: A portable benchmarking methodology for full-system simulators.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016
Hardware-Accelerated Cross-Architecture Full-System Virtualization.
TACO, 2016

Efficient asynchronous interrupt handling in a full-system instruction set simulator.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Application of Domain-aware Binary Fuzzing to Aid Android Virtual Machine Testing.
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2015

Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Experiences in speeding up computer vision applications on mobile computing platforms.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Free Rider: A Tool for Retargeting Platform-Specific Intrinsic Functions.
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

2014
Integrating profile-driven parallelism detection and machine-learning-based mapping.
TACO, 2014

Efficient code generation in a region-based dynamic binary translator.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Exploiting function similarity for code size reduction.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Variability of data dependences and control flow.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Measuring QoE of interactive workloads and characterising frequency governors on mobile devices.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Exploitation of GPUs for the Parallelisation of Probably Parallel Legacy Code.
Proceedings of the Compiler Construction - 23rd International Conference, 2014

Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation.
International Journal of Parallel Programming, 2013

Limits of region-based dynamic binary parallelization.
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Adaptive Source-Level Data Assignment to Dual Memory Banks.
ACM Trans. Embedded Comput. Syst., 2012

Statistical Performance Modeling in Functional Instruction Set Simulators.
ACM Trans. Embedded Comput. Syst., 2012

Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Compiling for automatically generated instruction set extensions.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

2011
Scalable multi-core simulation using parallel dynamic binary translation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Selecting the optimal system: automated design of application-specific systems-on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

A Learning-Based Approach to the Automated Design of MPSoC Networks.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
Workload characterization supporting the development of domain-specific compiler optimizations using decision trees for data mining.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

Empirical evaluation of data transformations for network infrastructure applications.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.
Proceedings of the CGO 2010, 2010

Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

C Compilers and Code Optimization for DSPs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Code transformation and instruction set extension.
ACM Trans. Embedded Comput. Syst., 2009

Towards a holistic approach to auto-parallelization: integrating profile-driven parallelism detection and machine-learning based mapping.
Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009

Reducing Training Time in a One-Shot Machine Learning-Based Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Fast source-level data assignment to dual memory banks.
Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, 2008

Fast cycle-approximate instruction set simulation.
Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, 2008

PDP: pen driven programming.
Proceedings of the 22nd British HCI Group Annual Conference on HCI 2008: People and Computers XXII: Culture, Creativity, Interaction, 2008

2007
A Cost-Aware Parallel Workload Allocation Approach Based on Machine Learning Techniques.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007

Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Fast compiler optimisation evaluation using code-feature based performance prediction.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Using Machine Learning to Focus Iterative Optimization.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

2005
A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems.
IEEE Trans. Parallel Distrib. Syst., 2005

Probabilistic source-level optimisation of embedded programs.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

2004
Compilation techniques for high-performance embedded systems with multiple processors.
PhD thesis, 2004

2003
Array recovery and high-level transformations for DSP applications.
ACM Trans. Embedded Comput. Syst., 2003

Compiler parallelization of C programs for multi-core DSPs with multiple address spaces.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2001
Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications.
Proceedings of the Compiler Construction, 10th International Conference, 2001

An empirical evaluation of high level transformations for embedded processors.
Proceedings of the 2001 International Conference on Compilers, 2001


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