Cheng-Han Lu
According to our database1,
Cheng-Han Lu authored at least 6 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2026
15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249µm<sup>2</sup> Bit-Cell, Dual-Port Access, and 51.2Gb/s Read Throughput for Automotive and Edge AI Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
CoRR, December, 2025
2023
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE International Conference on Big Data, 2022
2021
An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021