Hongce Zhang

According to our database, Hongce Zhang authored at least 31 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

SMT-Sweep: Word-Level Representation Unification for Hardware Verification.

Ziyi Yang, Guangyu Hu, Mingkai Miao, Changyuan Yu, Hongce Zhang

CoRR, July, 2025

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2025

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis.

Chen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang

CoRR, April, 2025

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie

CoRR, April, 2025

Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

Word-Level Counterexample Reduction Methods for Hardware Verification.

Zhiyuan Yan, Hongce Zhang

Proceedings of the Design, Automation & Test in Europe Conference, 2025

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.

Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie

CoRR, 2024

Word-Level Augmentation of Formal Proof by Learning from Simulation Traces.

Zhiyuan Yan, Hongce Zhang

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction.

Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis.

Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction.

Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

r-map: Relating Implementation and Specification in Hardware Refinement Checking.

Wenji Fang, Guangyu Hu, Hongce Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie

CoRR, 2023

Addressing Variable Dependency in GNN-based SAT Solving.

Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang

CoRR, 2023

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification.

Wenji Fang, Hongce Zhang

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking.

Guangyu Hu, Wei Zhang, Hongce Zhang

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms.

Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021

Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking.

Hongce Zhang, Aarti Gupta, Sharad Malik

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2021

Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables.

Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Pono: A Flexible and Extensible SMT-Based Model Checker.

Makai Mann, Ahmed Irfan, Florian Lonsing, Yahan Yang, Hongce Zhang, Kristopher Brown, Aarti Gupta, Clark W. Barrett

Proceedings of the Computer Aided Verification - 33rd International Conference, 2021

2020

Synthesizing Environment Invariants for Modular Hardware Verification.

Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2020

In Search for a SAT-friendly Binarized Neural Network Architecture.

Nina Narodytska, Hongce Zhang, Aarti Gupta, Toby Walsh

Proceedings of the 8th International Conference on Learning Representations, 2020

Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis.

Hongce Zhang, Maxwell Shinn, Aarti Gupta, Arie Gurfinkel, Nham Le, Nina Narodytska

Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020

2019

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification.

Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik

ACM Trans. Design Autom. Electr. Syst., 2019

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions.

Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2019

2018

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification.

Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

2016

A hardware-based technique for efficient implicit information flow tracking.

Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek

Proceedings of the 35th International Conference on Computer-Aided Design, 2016