Caroline Trippel

Orcid: 0000-0002-5776-1121

According to our database1, Caroline Trippel authored at least 29 papers between 2015 and 2024.

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Bibliography

2024
NL2FOL: Translating Natural Language to First-Order Logic for Logical Fallacy Detection.
CoRR, 2024

Model Selection for Latency-Critical Inference Serving.
Proceedings of the Nineteenth European Conference on Computer Systems, 2024

2023
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time.
CoRR, 2023

G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

nl2spec: Interactively Translating Unstructured Natural Language to Temporal Logics with Large Language Models.
Proceedings of the Computer Aided Verification - 35th International Conference, 2023

2022
Dynamic Network Adaptation at Inference.
CoRR, 2022

Axiomatic hardware-software contracts for security.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

RecShard: statistical feature-based memory optimization for industry-scale neural recommendation.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Relational Models of Microarchitectures for Formal Security Analyses.
CoRR, 2021

Analysis and Mitigations of Reverse Engineering Attacks on Local Feature Descriptors.
CoRR, 2021

Porcupine: a synthesizing compiler for vectorized homomorphic encryption.
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

Understanding and Improving Failure Tolerant Training for Deep Learning Recommendation with Partial Recovery.
Proceedings of the Fourth Conference on Machine Learning and Systems, 2021

Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
Proceedings of the Formal Methods in Computer Aided Design, 2021

Mitigating Reverse Engineering Attacks on Local Feature Descriptors.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

RecSSD: near data processing for solid state drive based recommendation inference.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
CPR: Understanding and Improving Failure Tolerant Training for Deep Learning Recommendation with Partial Recovery.
CoRR, 2020

SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach.
IEEE Micro, 2019

2018
Full-Stack Memory Model Verification with TriCheck.
IEEE Micro, 2018

MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols.
CoRR, 2018

CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification.
Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

2017
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design.
CoRR, 2016

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings.
CoRR, 2016

2015
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015


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