In-Chul Jeong

According to our database, In-Chul Jeong authored at least 4 papers between 2009 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN.

Jinhoon Hyun, In-Chul Jeong, Shinho Chu, Jaemyung Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

2025

GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning.

Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2023

A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement.

Woongrae Kim, Chulmoon Jung, Seong Nyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Oh-Yong Jung, Joonwoo Choi, Sanga Hyun, Mankeun Kang, Sangho Lee, Dohong Kim, Sanghyun Ku, Donhyun Choi, Nogeun Joo, Sangwoo Yoon, Junseok Noh, Byeongyong Go, Cheolhoe Kim, Sunil Hwang, Mihyun Hwang, Seol-Min Yi, Hyungmin Kim, Sanghyuk Heo, Yeonsu Jang, Kyoungchul Jang, Shinho Chu, Yoonna Oh, Kwidong Kim, Junghyun Kim, Soohwan Kim, Jeongtae Hwang, Sangil Park, Junphyo Lee, In-Chul Jeong, Joohwan Cho, Jonghwan Kim

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2009

1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.

Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim

Proceedings of the IEEE International Solid-State Circuits Conference, 2009