Kinam Kim

According to our database1, Kinam Kim authored at least 29 papers between 2002 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions the development of high-density dynamic random access memory.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015

1.1 Silicon technologies and solutions for the data-driven world.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012
A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Future silicon technology.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
The Forgotten.
Proceedings of the SIGGRAPH Asia 2011 Computer Animation Festival, 2011

2010
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits, 2010

2009
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits, 2009

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009

1.2V 1.6Gb/s 56nm 6F<sup>2</sup> 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput.
IEEE J. Solid State Circuits, 2008

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array.
IEEE J. Solid State Circuits, 2008

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
IEEE J. Solid State Circuits, 2007


The future outlook of memory devices.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
Enhanced write performance of a 64-mb phase-change random access memory.
IEEE J. Solid State Circuits, 2006

2005
Electrical properties of highly reliable 32Mb FRAM with advanced capacitor technology.
Microelectron. Reliab., 2005

Chohon.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2005

An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Emerging memory technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Integration technology for ferroelectric memory devices.
Microelectron. Reliab., 2003

2002
DRAM reliability.
Microelectron. Reliab., 2002

The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon.
Microelectron. Reliab., 2002


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