Kinam Kim
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Bibliography
2022
2018
Proceedings of the Computational Science/Intelligence & Applied Informatics, 2018
2016
Vision-Based Object-Centric Safety Assessment Using Fuzzy Inference: Monitoring Struck-By Accidents with Moving Objects.
J. Comput. Civ. Eng., 2016
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015
Inf. Sci., 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Proceedings of the Symposium on Applied Computing, 2014
2012
A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Proceedings of the SIGGRAPH Asia 2011 Computer Animation Festival, 2011
Proceedings of the 20th ACM Conference on Information and Knowledge Management, 2011
2010
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits, 2010
2009
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits, 2009
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009
1.2V 1.6Gb/s 56nm 6F<sup>2</sup> 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
2005
Electrical properties of highly reliable 32Mb FRAM with advanced capacitor technology.
Microelectron. Reliab., 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2005
An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2003
Microelectron. Reliab., 2003
A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme.
IEEE J. Solid State Circuits, 2003
2002
The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon.
Microelectron. Reliab., 2002
A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme.
IEEE J. Solid State Circuits, 2002
2000
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit.
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
1996
IEEE J. Solid State Circuits, 1996