Iyad Rayane

According to our database1, Iyad Rayane authored at least 6 papers between 1999 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

1999
A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

On-Line BIST for Testing Analog Circuits.
Proceedings of the IEEE International Conference On Computer Design, 1999

Automatic Design of Optimal Concurrent Fault Detector for Linear Analog Systems.
Proceedings of the Digest of Papers: FTCS-29, 1999

A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection.
Proceedings of the 1999 Design, 1999


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