Claire Fenouillet-Béranger

According to our database1, Claire Fenouillet-Béranger authored at least 23 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Radar-Based Human Activity Acquisition, Classification and Recognition Towards Elderly Fall Prediction.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2018
Role of synaptic variability in spike-based neuromorphic circuits with unsupervised learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.
Proceedings of the 47th European Solid-State Device Research Conference, 2017


2016


Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Towards high density 3D interconnections.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization.
Proceedings of the 45th European Solid State Device Research Conference, 2015

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Intermediate BEOL process influence on power and performance for 3DVLSI.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Novel back-biased UTBB lateral SCR for FDSOI ESD protections.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

New parameter extraction method based on split C-V for FDSOI MOSFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2010
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Process dependence of BTI reliability in advanced HK MG stacks.
Microelectron. Reliab., 2009



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