Philippe Flatresse

According to our database1, Philippe Flatresse authored at least 32 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 0.021mm<sup>2</sup> PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI.
Integr., 2020

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI.
CoRR, 2020

2018
A 2.5μW 0.0067mm<sup>2</sup> automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Resilient automotive products through process, temperature and aging compensation schemes.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.
IEEE J. Solid State Circuits, 2014


27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency.
Proceedings of the Design, Automation and Test in Europe, 2013


2012
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.
J. Low Power Electron., 2012

2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Bottom-up digital system-level reliability modeling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2006
Electro-thermal short pulsed simulation for SOI technology.
Microelectron. Reliab., 2006

2002
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002


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