Florian Klemme

Orcid: 0000-0002-0148-0523

According to our database1, Florian Klemme authored at least 23 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Approximation- and Quantization-Aware Training for Graph Neural Networks.
IEEE Trans. Computers, February, 2024

2023
Transistor Self-Heating-Aware Synthesis for Reliable Digital Circuit Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-informed Tree-based Graph Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Robust Pattern Generation for Small Delay Faults Under Process Variations.
Proceedings of the IEEE International Test Conference, 2023

Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Design Automation for Cryogenic CMOS Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors All the Way up Processors.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Scalable Machine Learning to Estimate the Impact of Aging on Circuits Under Workload Dependency.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Variability-Aware Approximate Circuit Synthesis via Genetic Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU.
IEEE Trans. Computers, 2022

On Extracting Reliability Information from Speed Binning.
Proceedings of the IEEE European Test Symposium, 2022


Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired Algorithms.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Machine Learning for Circuit Aging Estimation under Workload Dependency.
Proceedings of the IEEE International Test Conference, 2021

2020
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Cell Library Characterization using Machine Learning for Design Technology Co-Optimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


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