Jatin Chhugani

According to our database1, Jatin Chhugani authored at least 37 papers between 2000 and 2016.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
Matrix Factorization at Scale: a Comparison of Scientific Data Analytics in Spark and C+MPI Using Three Case Studies.
CoRR, 2016

A Multi-Platform Evaluation of the Randomized CX Low-Rank Matrix Factorization in Spark.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Matrix factorizations at scale: A comparison of scientific data analytics in spark and C+MPI using three case studies.
Proceedings of the 2016 IEEE International Conference on Big Data, 2016

2015
Can traditional programming bridge the ninja performance gap for parallel computing applications?
Commun. ACM, 2015

2012
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing.
IEEE Micro, 2012

CloudRAMSort: fast and efficient large-scale distributed RAM sort on shared-nothing cluster.
Proceedings of the ACM SIGMOD International Conference on Management of Data, 2012

Large-scale energy-efficient graph traversal: a path to efficient data-intensive supercomputing.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

Billion-particle SIMD-friendly two-point correlation on large-scale HPC cluster systems.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

GPP-Grep: High-Speed Regular Expression Processing Engine on General Purpose Processors.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2012

Can traditional programming bridge the Ninja performance gap for parallel computing applications?
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Fast and Efficient Graph Traversal Algorithm for CPUs: Maximizing Single-Node Efficiency.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

2011
Designing fast architecture-sensitive tree search on modern multicore/many-core processors.
ACM Trans. Database Syst., 2011

PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors.
PVLDB, 2011

Fast Updates on Read-Optimized Databases Using Multi-Core CPUs.
PVLDB, 2011

Fast Updates on Read-Optimized Databases Using Multi-Core CPUs
CoRR, 2011

High-performance lattice QCD for multi-core based parallel systems using a cache-friendly hybrid threaded-MPI approach.
Proceedings of the Conference on High Performance Computing Networking, 2011

2010
Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort.
Proceedings of the ACM SIGMOD International Conference on Management of Data, 2010

FAST: fast architecture sensitive tree search on modern CPUs and GPUs.
Proceedings of the ACM SIGMOD International Conference on Management of Data, 2010

PLEdestrians: A Least-Effort Approach to Crowd Simulation.
Proceedings of the 2010 Eurographics/ACM SIGGRAPH Symposium on Computer Animation, 2010

3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs.
Proceedings of the Conference on High Performance Computing Networking, 2010

Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures.
IEEE Trans. Vis. Comput. Graph., 2009

Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs.
PVLDB, 2009

ClearPath: highly parallel collision avoidance for multi-agent simulation.
Proceedings of the 2009 ACM SIGGRAPH/Eurographics Symposium on Computer Animation, 2009

Interactive Modeling, Simulation and Control of Large-Scale Crowds and Traffic.
Proceedings of the Motion in Games, Second International Workshop, 2009

2008
Efficient implementation of sorting on multi-core SIMD CPU architecture.
PVLDB, 2008

Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications.
Proceedings of the IEEE, 2008

Second Life and the New Generation of Virtual Worlds.
IEEE Computer, 2008

Atomic Vector Operations on Chip Multiprocessors.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Geometry engine optimization: cache friendly compressed representation of geometry.
Proceedings of the 2007 Symposium on Interactive 3D Graphics, 2007

Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2005
vLOD: High-Fidelity Walkthrough of Large Virtual Environments.
IEEE Trans. Vis. Comput. Graph., 2005

2004
Compressing Large Boolean Matrices using Reordering Techniques.
Proceedings of the (e)Proceedings of the Thirtieth International Conference on Very Large Data Bases, VLDB 2004, Toronto, Canada, August 31, 2004

2003
ISOSLIDER: A System for Interactive Exploration of Isosurfaces.
Proceedings of the VisSym 2003, 2003

Budget sampling of parametric surface patches.
Proceedings of the 2003 Symposium on Interactive 3D Graphics, 2003

2001
View-dependent adaptive tessellation of spline surfaces.
Proceedings of the 2001 Symposium on Interactive 3D Graphics, 2001

2000
Compression Tolerant Watermarking for Image Verification.
Proceedings of the 2000 International Conference on Image Processing, 2000


  Loading...