Jenn-Shiang Lai

According to our database¹, Jenn-Shiang Lai authored at least 8 papers between 1993 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2020

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

2018

A channel-sharable built-in self-test scheme for multi-channel DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

A hybrid built-in self-test scheme for DRAMs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

1994

Neural Networks for Optimization Problems in Graph Theory.

[BibT_eX]

[DOI]

Jenn-Shiang Lai

Sy-Yen Kuo

Ing-Yi Chen

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Artificial Neural Networks for the Bipartite and K-partite Subgraph Problems.

[BibT_eX]

[DOI]

Jenn-Shiang Lai

Young-Ja Ko

Sy-Yen Kuo

Proceedings of the PARLE '93, 1993

Jenn-Shiang Lai

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