Wei Wu

Affiliations:
  • Intel Research Laboratory, Hillsboro, OR, USA
  • University of California Riverside, Department of Electrical Engineering, CA, USA (PhD 2008)


According to our database1, Wei Wu authored at least 23 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Entropy loss in PUF-based key generation schemes: The repetition code pitfall.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013
A Spatial Majority Voting Technique to Reduce Error Rate of Physically Unclonable Functions.
Proceedings of the Trusted Systems - 5th International Conference, 2013

2012
Direct Compare of Information Coded With Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A practical device authentication scheme using SRAM PUFs.
J. Cryptogr. Eng., 2012

2011
Adaptive Cache Design to Enable Reliable Low-Voltage Operation.
IEEE Trans. Computers, 2011

A Practical Device Authentication Scheme Using SRAM PUFs.
Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011

Energy-efficient cache design using variable-strength error-correcting codes.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
Reducing cache power with low-cost, multi-bit error-correcting codes.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Improving cache lifetime reliability at ultra-low voltages.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation.
J. Low Power Electron., 2008

FEKIS: a fast architecture-level thermal analyzer for online thermal regulation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Efficient power modeling and software thermal sensing for runtime temperature monitoring.
ACM Trans. Design Autom. Electr. Syst., 2007

Improving the reliability of on-chip data caches under process variations.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Fast Thermal Simulation for Runtime Temperature Tracking and Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reduce Register Files Leakage Through Discharging Cells.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A systematic method for functional unit power estimation in microprocessors.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Dynamic Co-allocation of Level One Caches.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fast thermal simulation for architecture level dynamic thermal management.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.
Proceedings of the 2005 Design, 2005

2004
Assertion-based power/performance analysis of network processor architectures.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004


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