Jérémie Crenne

According to our database1, Jérémie Crenne authored at least 19 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018
Model-based Design of Efficient LDPC Decoder Architectures.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2014
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices.
Embedded Systems Letters, 2014

Modeling dynamic partial reconfiguration in the dataflow paradigm.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

2013
Configurable memory security in embedded systems.
ACM Trans. Embedded Comput. Syst., 2013

Reconfigurable Data Planes for Scalable Network Virtualization.
IEEE Trans. Computers, 2013

2012
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Lightweight reconfiguration security services for AXI-based MPSoCs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Distributed Security for Communications and Memories in a Multiprocessor Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Efficient key-dependent message authentication in reconfigurable hardware.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
Scalable network virtualization using FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Ultra-Fast Downloading of Partial Bitstreams through Ethernet.
Proceedings of the Architecture of Computing Systems, 2009

2008
Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008


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