Jonathan Piat

According to our database1, Jonathan Piat authored at least 16 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
HW/SW co-design of a visual SLAM application.
J. Real Time Image Process., 2020

2016
FPGA design of EKF block accelerator for 3D visual SLAM.
Comput. Electr. Eng., 2016

FPGA based hardware acceleration of a BRIEF correlator module for a monocular SLAM application.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015
Real Time Vision System for Obstacle Detection and Localization on FPGA.
Proceedings of the Computer Vision Systems - 10th International Conference, 2015

2014
Modeling dynamic partial reconfiguration in the dataflow paradigm.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Physical Layer Multi-Core Prototyping - A Dataflow-Based Approach for LTE eNodeB
Lecture Notes in Electrical Engineering 171, Springer, ISBN: 978-1-4471-4209-6, 2013

Embedded vision-based SLAM: A model-driven approach.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
FPGA implementation of mono and stereo inverse perspective mapping for obstacle detection.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework.
J. Signal Process. Syst., 2011

2010
Modélisation flux de données et optimisation pour architecture multi-cœurs de motifs répétitifs. (Data flow modelling and optimization of loops for multi-core architectures).
PhD thesis, 2010

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Loop transformations for interface-based hierarchies IN SDF graphs.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
An Open Framework for Rapid Prototyping of Signal Processing Applications.
EURASIP J. Embed. Syst., 2009

Interface-based hierarchy for synchronous data-flow graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008
Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008


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