Cyrille Chavet
Orcid: 0000-0002-7993-4628
According to our database1,
Cyrille Chavet
authored at least 37 papers
between 2007 and 2021.
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Bibliography
2021
Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards.
J. Signal Process. Syst., 2021
Proceedings of the 4th IEEE 5G World Forum, 2021
2020
IEEE Trans. Circuits Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Neural Networks Learn. Syst., 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
2017
Efficient scalable hardware architecture for highly performant encoded neural networks.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2015
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories.
ACM J. Emerg. Technol. Comput. Syst., 2015
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
In-place memory mapping approach for optimized parallel hardware interleaver architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.
Proceedings of the IEEE International Conference on Acoustics, 2014
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
2013
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm.
IEEE Trans. Signal Process., 2013
Tech. Sci. Informatiques, 2013
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
On-chip implementation of memory mapping algorithm to support flexible decoder architecture.
Proceedings of the IEEE International Conference on Acoustics, 2013
A memory mapping approach for network and controller optimization in parallel interleaver architectures.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
A design approach dedicated to network-based and conflict-free parallel interleavers.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A methodology based on Transportation problem modeling for designing parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
A memory mapping approach for parallel interleaver design with multiples read and write accesses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Static Address Generation Easing: a design methodology for parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2010
2007
Synthèse automatique d'interfaces de communication matérielles pour la conception d'applications du domaine du traitement du signal. (Automatic synthesis of hardware communication interfaces for Data Signal Processing applications).
PhD thesis, 2007
CoRR, 2007
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 15th European Signal Processing Conference, 2007