Pascal Benoit
Orcid: 0000-0002-2945-5725
According to our database1,
Pascal Benoit
authored at least 104 papers
between 2001 and 2024.
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Bibliography
2024
IEEE Comput. Archit. Lett., 2024
2022
IACR Cryptol. ePrint Arch., 2022
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the Computer Security. ESORICS 2021 International Workshops, 2021
Vulnerability Assessment of the Rowhammer Attack Using Machine Learning and the gem5 Simulator - Work in Progress.
Proceedings of the SAT-CPS@CODASPY 2021, 2021
2020
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020
Proceedings of the Cross Reality and Data Science in Engineering, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers.
IEEE Access, 2019
Proceedings of the IEEE Sensors Applications Symposium, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
2018
J. Low Power Electron., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Microprocess. Microsystems, 2017
Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocess. Microsystems, 2017
SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGAs.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Emerg. Top. Comput., 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
Energy-efficient control through power mode placement with discrete DVFS and Body Bias.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
2014
Microelectron. Reliab., 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Comput. Sci. Inf. Syst., 2013
An OMNeT++ model of the control system of large-scale concentrator photovoltaic power plants: poster abstract.
Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques, 2013
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
2012
Proceedings of the 3rd IEEE PES Innovative Smart Grid Technologies Europe, 2012
Proceedings of the 1st International IEEE Symposium on Wireless Systems, 2012
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
What the term Agent stands for in the Smart Grid, Definition of Agents and Multi-Agent Systems from an Engineer's Perspective .
Proceedings of the Federated Conference on Computer Science and Information Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
IEEE Embed. Syst. Lett., 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
J. Low Power Electron., 2010
Int. J. Embed. Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in Homogeneous MPSoC systems.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Investigation of Digital Sensors for Variability Characterization on FPGAs.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfigurable Comput., 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Int. J. Reconfigurable Comput., 2008
Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008
2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005
Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004
2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002
2001
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001