Pascal Benoit

According to our database1, Pascal Benoit authored at least 89 papers between 2001 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
WHISPER: A Tool for Run-Time Detection of Side-Channel Attacks.
IEEE Access, 2020

2019
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers.
IEEE Access, 2019

Evaluation of SPN-Based Lightweight Crypto-Ciphers.
IEEE Access, 2019

FlexNode: a reconfigurable Internet of Things node for design evaluation.
Proceedings of the IEEE Sensors Applications Symposium, 2019

Edge-Computing Perspectives with Reconfigurable Hardware.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

2018
PoETE: A Method to Design Temperature-Aware Integrated Systems.
J. Low Power Electron., 2018

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Computing in the Fog with Reconfigurable Gateways.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA Implementation of Pattern Matching for Industrial Control Systems.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Fine-grained monitoring for self-aware embedded systems.
Microprocess. Microsystems, 2017

Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocess. Microsystems, 2017

SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGAs.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Embedded systems to high performance computing using STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Cost-Effective Design Strategies for Securing Embedded Processors.
IEEE Trans. Emerg. Top. Comput., 2016

Hardware security: From concept to application.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
A survey on security features in modern FPGAs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Adaptive Power monitoring for self-aware embedded systems.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Energy-efficient control through power mode placement with discrete DVFS and Body Bias.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Digital Right Management for IP Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Software testing and software fault injection.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs.
Microelectron. Reliab., 2014

Fault injection tools based on Virtual Machines.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Method for dynamic power monitoring on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Aging effects in FPGAs: an experimental analysis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Power management through DVFS and dynamic body biasing in FD-SOI circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embedded Comput. Syst., 2013

Fine-Grain Dynamic Energy Tracking for System on Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Multi-agent systems' asset for smart grid applications.
Comput. Sci. Inf. Syst., 2013

An OMNeT++ model of the control system of large-scale concentrator photovoltaic power plants: poster abstract.
Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques, 2013

Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012
Device-to-device communication for Smart Grid devices.
Proceedings of the 3rd IEEE PES Innovative Smart Grid Technologies Europe, 2012

SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

What the term Agent stands for in the Smart Grid, Definition of Agents and Multi-Agent Systems from an Engineer's Perspective .
Proceedings of the Federated Conference on Computer Science and Information Systems, 2012

Amplitude demodulation-based EM analysis of different RSA implementations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
Embedded Systems Letters, 2011

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Evaluation of a distributed fault handler method for MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Modular Framework for Multi-level Multi-device MPSoC Simulation.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

RAW Introduction.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Optimizing an Open-Source Processor for FPGAs: A Case Study.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An Introduction to Multi-Core System on Chip - Trends and Challenges.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips.
J. Low Power Electron., 2010

Run-time mapping for dynamic reconfiguration management in embedded systems.
IJES, 2010

Spatial EM jamming: A countermeasure against EM Analysis?
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A run-time distributed cooperative approach to optimize power consumption in MPSoCs.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Evaluating the impact of task migration in multi-processor systems-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Flexible and distributed real-time control on a 4G telecom MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem.
Proceedings of the Design, Automation and Test in Europe, 2010

An in-memory monitoring database for self adaptive MP2SoCs.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

D-Scale: A Scalable System-Level Dependable Method for MPSoCs.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfigurable Comput., 2009

An Adaptive Message Passing MPSoC Framework.
Int. J. Reconfigurable Comput., 2009

Adaptive energy-aware latency-constrained DVFS policy for MPSoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC.
Int. J. Reconfigurable Comput., 2008

Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

MPI-Based Adaptive Task Migration Support on the HS-Scale System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Bio-inspiration helps computers: A new machine.
Proceedings of the FPL 2008, 2008

Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008

2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005

Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Dynamic hardware multiplexing for coarse grain reconfigurable architectures.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004

2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002

2001
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001


  Loading...