Ji-Hoon Kim
Orcid: 0000-0002-9809-1339Affiliations:
- Ewha Womans University, Department of Electronic and Electrical Engineering, Smart Factory Multidisciplinary Program, Seoul, South Korea
- Chungnam National University, Department of Electronics Engineering, Daejeon, South Korea (2010 - 2016)
- KAIST, Daejeon, South Korea (PhD 2009)
According to our database1,
Ji-Hoon Kim
authored at least 50 papers
between 2006 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Proceedings of the International Conference on Electronics, Information, and Communication, 2025
Proceedings of the International Conference on Electronics, Information, and Communication, 2025
2024
Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-Time Memory Diagnostic Data Compression in Automotive SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Access, 2023
IEEE Access, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.
IEEE Trans. Computers, 2022
An Indoor-Monitoring LiDAR Sensor for Patients with Alzheimer Disease Residing in Long-Term Care Facilities.
Sensors, 2022
IEEE J. Solid State Circuits, 2022
SQNR-based Layer-wise Mixed-Precision Schemes with Computational Complexity Consideration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Machine Learning-based Wearable Bio-processor for Real-Time Blood Pressure Estimation.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Secure IC with Countermeasure to Unpowered Physical Attack using On-chip Photodiode and Charge Pump.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End.
IEEE Trans. Biomed. Circuits Syst., 2020
2019
IEEE J. Solid State Circuits, 2019
High-Speed Visual Target Identification for Low-Cost Wearable Brain-Computer Interfaces.
IEEE Access, 2019
Fast and Power-Analysis Resistant Ring Lizard Crypto-Processor Based on the Sparse Ternary Property.
IEEE Access, 2019
A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca<sup>2+</sup>-Probe-Based Fluorescence Recording and Electrical Recording.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Comput. Electr. Eng., 2018
A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.
Sensors, 2016
IEICE Electron. Express, 2016
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEICE Electron. Express, 2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of the Convergence and Hybrid Information Technology, 2011
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006