Ji-Hoon Kim

Orcid: 0000-0002-9809-1339

Affiliations:
  • Ewha Womans University, Department of Electronic and Electrical Engineering, Smart Factory Multidisciplinary Program, Seoul, South Korea
  • Chungnam National University, Department of Electronics Engineering, Daejeon, South Korea (2010 - 2016)
  • KAIST, Daejeon, South Korea (PhD 2009)


According to our database1, Ji-Hoon Kim authored at least 50 papers between 2006 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Optimized Distance Calculation Support for HBM PIM(Processing-In-Memory).
Proceedings of the International Conference on Electronics, Information, and Communication, 2025

Vector Similarity Search Acceleration using DRAM-based Processing-In-Memory (PIM).
Proceedings of the International Conference on Electronics, Information, and Communication, 2025

2024
Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Optimized Transform Entropy Decoding Architecture for VDC-M.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-Time Memory Diagnostic Data Compression in Automotive SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs.
IEEE Access, 2023

Complexity-Aware Layer-Wise Mixed-Precision Schemes With SQNR-Based Fast Analysis.
IEEE Access, 2023

High-Level AMBA Monitoring Platform for SoC Architecture Exploration.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

Hardware-Software Co-Design of AES-CCM for Bluetooth LE Security.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

Verilator-based Fast Verification Methodology for BLE MAC Hardware.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.
IEEE Trans. Computers, 2022

An Indoor-Monitoring LiDAR Sensor for Patients with Alzheimer Disease Residing in Long-Term Care Facilities.
Sensors, 2022

An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation.
IEEE J. Solid State Circuits, 2022

SQNR-based Layer-wise Mixed-Precision Schemes with Computational Complexity Consideration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Machine Learning-based Wearable Bio-processor for Real-Time Blood Pressure Estimation.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Post-Quantum Cryptography Coprocessor for RISC-V CPU Core.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

2021
A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

21.1 A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS Transceiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Secure IC with Countermeasure to Unpowered Physical Attack using On-chip Photodiode and Charge Pump.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020
A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End.
IEEE Trans. Biomed. Circuits Syst., 2020

2019
A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

High-Speed Visual Target Identification for Low-Cost Wearable Brain-Computer Interfaces.
IEEE Access, 2019

Fast and Power-Analysis Resistant Ring Lizard Crypto-Processor Based on the Sparse Ternary Property.
IEEE Access, 2019

A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca<sup>2+</sup>-Probe-Based Fluorescence Recording and Electrical Recording.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Memory-Reduced Non-Binary LDPC Decoding With Accumulative Bubble Check.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Secure circuit with optical energy harvesting against unpowered physical attacks.
Comput. Electr. Eng., 2018

A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.
Sensors, 2016

A new digital predistortion technique for analog beamforming systems.
IEICE Electron. Express, 2016

2012
Design of TETRA 2 turbo decoder with minimum memory hardware interleaver.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Memory reduced MAP decoding for double-binary turbo decoder.
IEICE Electron. Express, 2011

Design of TETRA Release 2 turbo decoder with low-complexity hardware interleaver.
Proceedings of the International SoC Design Conference, 2011

Design and Implementation of Turbo Decoder for TETRA Release 2 - TEDS.
Proceedings of the Convergence and Hybrid Information Technology, 2011

2009
Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Double-Binary Circular Turbo Decoding Based on Border Metric Encoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Duo-binary circular turbo decoder based on border metric encoding for WiMAX.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Long-Point FFT Processing Based on Twiddle Factor Table Reduction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Twiddle factor transformation for pipelined FFT processing.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Low-Power Hybrid Turbo Decoding Based on Reverse Calculation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006


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