Jie Zhang

Affiliations:
  • Google
  • Stanford University


According to our database1, Jie Zhang authored at least 16 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

2013
Carbon nanotube circuits: opportunities and challenges.
Proceedings of the Design, Automation and Test in Europe, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Carbon Nanotube Robust Digital VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Robust System Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Carbon nanotube circuits: Living with imperfections and variations.
Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010

2009
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
Proceedings of the Design, Automation and Test in Europe, 2009

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009

Carbon nanotube circuits in the presence of carbon nanotube density variations.
Proceedings of the 46th Design Automation Conference, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Proceedings of the 46th Design Automation Conference, 2009

2008
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008


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