Nishant Patil

According to our database1, Nishant Patil authored at least 23 papers between 2005 and 2018.

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Bibliography

2018
Motivation for and Evaluation of the First Tensor Processing Unit.
IEEE Micro, 2018

A domain-specific architecture for deep neural networks.
Commun. ACM, 2018

2017
In-Datacenter Performance Analysis of a Tensor Processing Unit.
CoRR, 2017


2016
Google's Neural Machine Translation System: Bridging the Gap between Human and Machine Translation.
CoRR, 2016

2012
Carbon Nanotube Robust Digital VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

2011
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Robust System Design.
IPSJ Trans. System LSI Design Methodology, 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Efficient FPGAs using nanoelectromechanical relays.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Carbon nanotube circuits: Living with imperfections and variations.
Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010

2009
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Imperfection-immune Carbon Nanotube digital VLSI.
Proceedings of the 27th International Conference on Computer Design, 2009

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
Proceedings of the Design, Automation and Test in Europe, 2009

Carbon nanotube circuits in the presence of carbon nanotube density variations.
Proceedings of the 46th Design Automation Conference, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Proceedings of the 46th Design Automation Conference, 2009

2008
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Signature Analyzer Design for Yield Learning Support.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
X-Tolerant Test Response Compaction.
IEEE Design & Test of Computers, 2005


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