Nishant Patil

According to our database, Nishant Patil authored at least 30 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings.

Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Understanding and Mitigating Hardware Failures in Deep Learning Training Systems.

Yi He, Mike Hutton, Steven Chan, Robert De Gruijl, Rama Govindaraju, Nishant Patil, Yanjing Li

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Area and Power Efficient Receiver for Narrowband Internet of Things Applications.

Nishant Patil, Sankaran Aniruddhan

Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023

2021

The Design Process for Google's Training Chips: TPUv2 and TPUv3.

Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson

IEEE Micro, 2021

Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product.

Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter C. Ma, Xiaoyu Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

A domain-specific supercomputer for training deep neural networks.

Norman P. Jouppi, Doe Hyun Yoon, George Kurian, Sheng Li, Nishant Patil, James Laudon, Cliff Young, David A. Patterson

Commun. ACM, 2020

Google's Training Chips Revealed: TPUv2 and TPUv3.

Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2018

Motivation for and Evaluation of the First Tensor Processing Unit.

Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson

IEEE Micro, 2018

A domain-specific architecture for deep neural networks.

Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson

Commun. ACM, 2018

2017

In-Datacenter Performance Analysis of a Tensor Processing Unit.

Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon

CoRR, 2017

In-Datacenter Performance Analysis of a Tensor Processing Unit.

Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016

Google's Neural Machine Translation System: Bridging the Gap between Human and Machine Translation.

Yonghui Wu, Mike Schuster, Zhifeng Chen, Quoc V. Le, Mohammad Norouzi, Wolfgang Macherey, Maxim Krikun, Yuan Cao, Qin Gao, Klaus Macherey, Jeff Klingner, Apurva Shah, Melvin Johnson, Xiaobing Liu, Lukasz Kaiser, Stephan Gouws, Yoshikiyo Kato, Taku Kudo, Hideto Kazawa, Keith Stevens, George Kurian, Nishant Patil, Wei Wang, Cliff Young, Jason Smith, Jason Riesa, Alex Rudnick, Oriol Vinyals, Greg Corrado, Macduff Hughes, Jeffrey Dean

CoRR, 2016

2012

Carbon Nanotube Robust Digital VLSI.

Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.

Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Robust System Design.

Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.

Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Efficient FPGAs using nanoelectromechanical relays.

Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Carbon nanotube circuits: Living with imperfections and variations.

Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.

Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra

Proceedings of the 47th Design Automation Conference, 2010

2009

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.

Jie Zhang, Nishant Patil, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Imperfection-immune Carbon Nanotube digital VLSI.

Nishant Patil, Subhasish Mitra

Proceedings of the 27th International Conference on Computer Design, 2009

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.

Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei

Proceedings of the Design, Automation and Test in Europe, 2009

Carbon nanotube circuits in the presence of carbon nanotube density variations.

Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra

Proceedings of the 46th Design Automation Conference, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.

Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 46th Design Automation Conference, 2009

2008

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.

Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.

Jie Zhang, Nishant Patil, Subhasish Mitra

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections.

Jie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.

Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 44th Design Automation Conference, 2007

2006

Signature Analyzer Design for Yield Learning Support.

Nishant Patil, Subhasish Mitra, Steven S. Lumetta

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

X-Tolerant Test Response Compaction.

Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil

IEEE Des. Test Comput., 2005