Hyungmin Cho

Orcid: 0000-0001-8705-7066

According to our database1, Hyungmin Cho authored at least 33 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers.
IEEE Access, 2023

FARNN: FPGA-GPU Hybrid Acceleration Platform for Recurrent Neural Networks.
IEEE Trans. Parallel Distributed Syst., 2022

ES4D: Accelerating Exact Similarity Search for High-Dimensional Vectors via Vector Slicing and In-SSD Computation.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Know Your Neighbor: Physically Locating Xeon Processor Cores on the Core Tile Grid.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping.
ACM Trans. Embed. Comput. Syst., 2021

Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement.
IEEE Access, 2021

SpecMCTS: Accelerating Monte Carlo Tree Search Using Speculative Tree Traversal.
IEEE Access, 2021

GPU-based acceleration of the Linear Complexity Test for random number generator testing.
J. Parallel Distributed Comput., 2019

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets.
IEEE Access, 2019

Corrections to "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects".
IEEE Access, 2019

Correction to "ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols".
IEEE Access, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FA3C: FPGA-Accelerated Deep Reinforcement Learning.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols.
IEEE Access, 2018

Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects.
IEEE Access, 2018

Transparent GPU memory management for DNNs.
Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018

System-Level Effects of Soft Errors in Uncore Components.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Understanding soft errors in uncore components.
Proceedings of the 52nd Annual Design Automation Conference, 2015

The resilience wall: Cross-layer solution strategies.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Rethinking error injection for effective resilience.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Gallager B Decoder on Noisy Hardware.
IEEE Trans. Commun., 2013

Quantitative evaluation of soft error injection techniques for robust system design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

ERSA: Error Resilient System Architecture for Probabilistic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Eigenmode BER based MU-MIMO scheduling for rate maximization with linear precoding and power allocation.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Probabilistic analysis of Gallager B faulty decoder.
Proceedings of IEEE International Conference on Communications, 2012

Robust System Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2011

Cross-layer error resilience for robust systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

ERSA: Error Resilient System Architecture for probabilistic applications.
Proceedings of the Design, Automation and Test in Europe, 2010

High recording density hard disk channel equalization using a bilinear recursive polynomial model.
IEICE Electron. Express, 2009

Dynamic data scratchpad memory management for a memory subsystem with an MMU.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007