Vikas Chandra

CoRR, 2024

Not All Weights Are Created Equal: Enhancing Energy Efficiency in On-Device Streaming Speech Recognition.

[BibT_eX]

[DOI]

CoRR, 2024

MVDiffusion++: A Dense High-resolution Multi-view Diffusion Model for Single or Sparse-view 3D Object Reconstruction.

[BibT_eX]

[DOI]

CoRR, 2024

Taming Mode Collapse in Score Distillation for Text-to-3D Generation.

[BibT_eX]

[DOI]

CoRR, 2024

SteinDreamer: Variance Reduction for Text-to-3D Score Distillation via Stein Identity.

[BibT_eX]

[DOI]

CoRR, 2024

2023

SqueezeSAM: User friendly mobile interactive segmentation.

[BibT_eX]

[DOI]

Balakrishnan Varadarajan

CoRR, 2023

EfficientSAM: Leveraged Masked Image Pretraining for Efficient Segment Anything.

[BibT_eX]

[DOI]

CoRR, 2023

On The Open Prompt Challenge In Conditional Audio Generation.

[BibT_eX]

[DOI]

CoRR, 2023

In-Context Prompt Editing For Conditional Audio Generation.

[BibT_eX]

[DOI]

CoRR, 2023

MiniGPT-v2: large language model as a unified interface for vision-language multi-task learning.

[BibT_eX]

[DOI]

Yunyang Xiong

Mohamed Elhoseiny

CoRR, 2023

FoleyGen: Visually-Guided Audio Generation.

[BibT_eX]

[DOI]

CoRR, 2023

Stack-and-Delay: a new codebook pattern for music generation.

[BibT_eX]

[DOI]

CoRR, 2023

Enhance audio generation controllability through representation similarity regularization.

[BibT_eX]

[DOI]

CoRR, 2023

Folding Attention: Memory and Power Optimization for On-Device Transformer-based Streaming Speech Recognition.

[BibT_eX]

[DOI]

CoRR, 2023

TODM: Train Once Deploy Many Efficient Supernet-Based RNN-T Compression For On-device ASR Models.

[BibT_eX]

[DOI]

CoRR, 2023

Mixture-of-Supernets: Improving Weight-Sharing Supernet Training with Architecture-Routed Mixture-of-Experts.

[BibT_eX]

[DOI]

Muhammad Abdul-Mageed

Laks V. S. Lakshmanan

CoRR, 2023

LLM-QAT: Data-Free Quantization Aware Training for Large Language Models.

[BibT_eX]

[DOI]

CoRR, 2023

Fast Point Cloud Generation with Straight Flows.

[BibT_eX]

[DOI]

Qiang Liu

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Towards Zero-Shot Multilingual Transfer for Code-Switched Responses.

[BibT_eX]

[DOI]

Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2023

Revisiting Sample Size Determination in Natural Language Understanding.

[BibT_eX]

[DOI]

Ernie Chang

Muhammad Hassan Rashid

Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023

2022

Introduction to the Special Section on Energy-Efficient AI Chips.

[BibT_eX]

[DOI]

Yiran Chen

Sungjoo Yoo

ACM Trans. Design Autom. Electr. Syst., 2022

Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications.

[BibT_eX]

[DOI]

IEEE Micro, 2022

PathFusion: Path-consistent Lidar-Camera Deep Feature Fusion.

[BibT_eX]

[DOI]

Qiang Liu

CoRR, 2022

SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.

[BibT_eX]

[DOI]

CoRR, 2022

XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.

[BibT_eX]

[DOI]

CoRR, 2022

LiCo-Net: Linearized Convolution Network for Hardware-efficient Keyword Spotting.

[BibT_eX]

[DOI]

CoRR, 2022

Feature-Align Network with Knowledge Distillation for Efficient Denoising.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision Workshops, 2022

Streaming parallel transducer beam search with fast slow cascaded encoders.

[BibT_eX]

[DOI]

Proceedings of the Interspeech 2022, 2022

DepthShrinker: A New Compression Paradigm Towards Boosting Real-Hardware Efficiency of Compact Neural Networks.

[BibT_eX]

[DOI]

Yingyan Lin

Proceedings of the International Conference on Machine Learning, 2022

NASViT: Neural Architecture Search for Efficient Vision Transformers with Gradient Conflict aware Supernet Training.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Conference on Learning Representations, 2022

Omni-Sparsity DNN: Fast Sparsity Optimization for On-Device Streaming E2E ASR Via Supernet.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2022

Contrastive quant: quantization makes stronger contrastive learning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

ScaleNAS: Multi-Path One-Shot NAS for Scale-Aware High-Resolution Representation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Automated Machine Learning, 2022

2021

Low-Rank+Sparse Tensor Compression for Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2021

Noisy Training Improves E2E ASR for the Edge.

[BibT_eX]

[DOI]

CoRR, 2021

Improve Vision Transformers Training by Suppressing Over-smoothing.

[BibT_eX]

[DOI]

CoRR, 2021

Feature-Align Network and Knowledge Distillation for Efficient Denoising.

[BibT_eX]

[DOI]

CoRR, 2021

AlphaNet: Improved Training of Supernet with Alpha-Divergence.

[BibT_eX]

[DOI]

CoRR, 2021

EVRNet: Efficient Video Restoration on Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021

DIAN: Differentiable Accelerator-Network Co-Search Towards Maximal DNN Efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Collaborative Training of Acoustic Encoders for Speech Recognition.

[BibT_eX]

[DOI]

Proceedings of the Interspeech 2021, 22nd Annual Conference of the International Speech Communication Association, Brno, Czechia, 30 August, 2021

AlphaNet: Improved Training of Supernets with Alpha-Divergence.

[BibT_eX]

[DOI]

Proceedings of the 38th International Conference on Machine Learning, 2021

Double-Win Quant: Aggressively Winning Robustness of Quantized Deep Neural Networks via Random Precision Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the 38th International Conference on Machine Learning, 2021

CPT: Efficient Deep Neural Network Training via Cyclic Precision.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Learning Representations, 2021

Memory-Efficient Speech Recognition on Smart Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2021

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

AttentiveNAS: Improving Neural Architecture Search via Attentive Sampling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

KeepAugment: A Simple Information-Preserving Data Augmentation Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Mind mappings: enabling efficient algorithm-accelerator mapping space search.

[BibT_eX]

[DOI]

Christopher W. Fletcher

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization.

[BibT_eX]

[DOI]

Meng Li

Yilei Li

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

NASGEM: Neural Architecture Search via Graph Embedding Method.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020

ScaleNAS: One-Shot Learning of Scale-Aware Representations for Visual Recognition.

[BibT_eX]

[DOI]

CoRR, 2020

Can Temporal Information Help with Contrastive Self-Supervised Learning?

[BibT_eX]

[DOI]

CoRR, 2020

DNA: Differentiable Network-Accelerator Co-Search.

[BibT_eX]

[DOI]

CoRR, 2020

NASGEM: Neural Architecture Search via Graph Embedding Method.

[BibT_eX]

[DOI]

CoRR, 2020

Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization.

[BibT_eX]

[DOI]

CoRR, 2020

RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

One Weight Bitwidth to Rule Them All.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Energy-Aware Neural Architecture Optimization with Fast Splitting Steepest Descent.

[BibT_eX]

[DOI]

CoRR, 2019

HERALD: Optimizing Heterogeneous DNN Accelerators for Edge Devices.

[BibT_eX]

[DOI]

CoRR, 2019

2018

Federated Learning with Non-IID Data.

[BibT_eX]

[DOI]

CoRR, 2018

CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs.

[BibT_eX]

[DOI]

Naveen Suda

CoRR, 2018

Not All Ops Are Created Equal!

[BibT_eX]

[DOI]

Naveen Suda

CoRR, 2018

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Guest Editors' Introduction: Computing in the Dark Silicon Era.

[BibT_eX]

[DOI]

Muhammad Shafique

Siddharth Garg

IEEE Des. Test, 2017

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2017

Hello Edge: Keyword Spotting on Microcontrollers.

[BibT_eX]

[DOI]

CoRR, 2017

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.

[BibT_eX]

[DOI]

CoRR, 2017

Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations.

[BibT_eX]

[DOI]

Naveen Suda

CoRR, 2017

Exploiting data-dependence and Flip-Flop asymmetry for zero-overhead system soft error mitigation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um<sup>2</sup> 6T bitcell in a 16nm FinFET CMOS process.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Resiliency in dynamically power managed designs.

[BibT_eX]

[DOI]

Rob Aitken

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.

[BibT_eX]

[DOI]

Mojtaba Ebrahimi

Adrian Evans

Mehdi Baradaran Tahoori

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Circuit design perspectives for Ge FinFET at 10nm and beyond.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Evaluating and exploiting impacts of dynamic power management schemes on system reliability.

[BibT_eX]

[DOI]

Puneet Gupta

Proceedings of the 2015 International Conference on Compilers, 2015

2014

Guest Editorial - Special Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013).

[BibT_eX]

[DOI]

José M. de la Rosa

John W. M. Rogers

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

BTI-Gater: An Aging-Resilient Clock Gating Methodology.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Physical design and FinFETs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Modeling SRAM dynamic VMIN.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

HotChips security tutorial.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Mobile hardware security.

[BibT_eX]

[DOI]

Rob Aitken

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Cross layer resiliency in real world.

[BibT_eX]

[DOI]

Subhasish Mitra

Chen-Yong Cher

Silvia Melitta Müller

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Monitoring Reliability in Embedded Processors - A Multi-layer View.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Quantifying workload dependent reliability in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012).

[BibT_eX]

[DOI]

Shanthi Pavan

John W. M. Rogers

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

SlackProbe: a low overhead in situ on-line timing slack monitoring methodology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write V<sub>MIN</sub>.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

The past present and future of design-technology co-optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Design benchmarking to 7nm with FinFET predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Exploring sub-20nm FinFET design with predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Advanced memory topics.

[BibT_eX]

[DOI]

Tom Andre

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Circuit-level delay modeling considering both TDDB and NBTI.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Analysis of Beliefs of Survivors of the 7/7 London Bombings: Application of a Formal Model for Contagion of Mental States.

[BibT_eX]

[DOI]

Tibor Bosse

Eve Mitleton-Kelly

C. Natalie van der Wal

Proceedings of the Neural Information Processing - 18th International Conference, 2011

Dynamic write limited minimum operating voltage for nanoscale SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

On the impact of gate oxide degradation on SRAM dynamic and static write-ability.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A black box method for stability analysis of arbitrary SRAM cell structures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

TIMBER: Time borrowing and error relaying for online timing error resilience.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Analytical model for TDDB-based performance degradation in combinational logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs.

[BibT_eX]

[DOI]

Cezary Pietrzyk

Proceedings of the Design, Automation and Test in Europe, 2010

Probabilistic spreading of information in a spatial network.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer Information Systems and Industrial Management Applications, 2010

2009

Robust Circuit Design: Challenges and Solutions.

[BibT_eX]

[DOI]

Saurabh K. Tiwary

Amith Singhee

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Designing dependable multicore system with unreliable components.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Impact of voltage scaling on nanoscale SRAM reliability.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Memory trends.

[BibT_eX]

[DOI]

Tom Andre

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2005

Layout techniques for FPGA switch blocks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

2004

A low power approach to system level pipelined interconnect design.

[BibT_eX]

[DOI]

Anthony Xu

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

A power aware system level interconnect design methodology for latency-insensitive systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

An Interconnect Channel Design Methodology for High Performance Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.

[BibT_eX]

[DOI]

Gary D. Carpenter

Jeffrey L. Burns

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Heterogeneous Programmable Logic Block Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

FPGA switch block layout and evaluation.

[BibT_eX]

[DOI]