Jin-Mei Lai

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2023
EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Accurate Area Model for FPGA Circuits at Advanced Technologies.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning.
IEEE Geosci. Remote. Sens. Lett., 2022

AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design.
Integr., 2022

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure.
IEICE Trans. Inf. Syst., 2021

FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA.
IEICE Trans. Inf. Syst., 2021

TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A Tile-based Interconnect Model for FPGA Architecture Exploration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

INTB: A New FPGA Interconnect Model for Architecture Exploration.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Stochastic Loss Function.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Analytical-based Hybrid Algorithm for FPGA Placement.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Research on the impact of different benchmark circuits on the representative path in FPGAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Design and implementation of Serial ATA pbysical layer on FPGA.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Research on Area Modeling Methodology for FPGA Interconnect Circuits.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An FPGA-based log-structure Flash memory system for space exploration.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Low-delay Configurable Register for FPGA.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Balance of memory footprint and runtime for high-density routing in large-scale FPGAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Web-based Waveform Viewer for BR0101 Chip Testing Platform.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Polymorphic Circuit Interoperability Framework.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Design of a power efficient self-adaptive LVDS driver.
IEICE Electron. Express, 2018

A SA-based parallel method for FPGA placement.
IEICE Electron. Express, 2018

2017
Flux balance analysis predicts Warburg-like effects of mouse hepatocyte deficient in miR-122a.
PLoS Comput. Biol., 2017

FPGA-based convolution neural network for traffic sign recognition.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A deep research on the chip verification platform based on network.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Prototyping design of a flexible DSP block with pipeline structure for FPGA.
IEICE Electron. Express, 2016

A universal automatic on-chip measurement of FPGA's internal setup and hold times.
IEICE Electron. Express, 2016

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
A new automatic method for testing interconnect resources in FPGAs based on general routing matrix.
IEICE Electron. Express, 2015

Design and implementation of clock network for nanometer FPGA.
IEICE Electron. Express, 2015

A power efficient current-mode differential driver for FPGAs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Iterative optimization algorithm for sound localization.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An Architecture Independent Packing Method for LUT-based Commercial FPGA.
J. Comput., 2014

Novel FPGA clock network with low latency and skew (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Optimisation of Mixed Polarity Reed-Muller Functions.
J. Softw., 2013

Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions.
J. Comput., 2013

A hierarchical parallel evolvable hardware based on network on chip.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A novel net-partition-based multithread FPGA routing method.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel multithread routing method for FPGAs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

FPGA bitstream compression and decompression using LZ and golomb coding (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

The timing control design of 65nm block RAM in FPGA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high throughput FPGA embedded DSP architecture design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Improved unified interconnect unit for high speed and scalable FPGA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Weight-based FPGA placement algorithm with wire effect considered.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high-resolution TDC implemented in a 90nm process FPGA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A novel memristor-based rSRAM structure for multiple-bit upsets immunity.
IEICE Electron. Express, 2012

A novel full coverage test method for CLBs in FPGA (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Finite State Machine Synthesis Based on Relay-Based Algorithm.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
FPGA Interconnect Architecture Exploration Based on a Statistical Model.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

The design and verification of SEU-hardened configurable DFF.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA interconnect timing library based on the statistical method.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Research on design method of scalable Configurable IP Core.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2009
Inferring a transcriptional regulatory network of the cytokinesis-related genes by network component analysis.
BMC Syst. Biol., 2009

POINeT: protein interactome with sub-network analysis and hub prioritization.
BMC Bioinform., 2009

Self-adaptive evolution of complex logic circuits.
Proceedings of the 2009 IEEE Workshop on Evolvable and Adaptive Hardware, 2009

A novel minloop SB design to improve FPGA routability.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

A delay-optimized universal FPGA routing architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
A high-performance reconfigurable VLSI architecture for vbsme in H.264.
IEEE Trans. Consumer Electron., 2008

Ortholog-based protein-protein interaction prediction and its application to inter-species interactions.
BMC Bioinform., 2008

High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A high-performance reconfigurable 2-D transform architecture for H.264.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

PhosphoPOINT: a comprehensive human kinase interactome and phospho-protein database.
Proceedings of the ECCB'08 Proceedings, 2008

Design and implementation of the configuration circuit for FDP FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A novel dynamic reconfigurable VLSI architecture for H.264 transforms.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Detection of the inferred interaction network in hepatocellular carcinoma from EHCO (Encyclopedia of Hepatocellular Carcinoma genes Online).
BMC Bioinform., 2007

2005
Design of A 2.4-GHz integrated frequency synthesizer.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A design of high speed double precision floating point adder using macro modules.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Iterative solution of ODE-PDE-AE systems for RF circuit simulation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


  Loading...