Jiwoo Pak

According to our database, Jiwoo Pak authored at least 9 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A graph placement methodology for fast chip design.

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim M. Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, Jeff Dean

Nat., 2021

2020

Chip Placement with Deep Reinforcement Learning.

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe W. J. Jiang, Ebrahim M. Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Anand Babu, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, Jeff Dean

CoRR, 2020

2015

Electromigration-aware redundant via insertion.

Jiwoo Pak, Bei Yu, David Z. Pan

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs.

Jiwoo Pak, Sung Kyu Lim, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs.

Jiwoo Pak, Sung Kyu Lim, David Z. Pan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Electromigration-aware routing for 3D ICs with stress-aware EM modeling.

Jiwoo Pak, Sung Kyu Lim, David Z. Pan

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.

David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs.

Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.

Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011