Xin Zhao

Affiliations:
  • Georgia Institute of Technology, Atlanta, GA, USA


According to our database1, Xin Zhao authored at least 21 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

2013
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Reliable clock and power delivery network design for three-dimensional integrated circuits.
PhD thesis, 2012

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012


TSV array utilization in low-power 3D clock network design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Buffered clock tree sizing for skew minimization under power and thermal budgets.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Slew-aware clock tree design for reliable subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Pre-bond testable low-power clock tree design for 3D stacked ICs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Buffered clock tree synthesis for 3D ICs under thermal variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007


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