Moongon Jung

According to our database1, Moongon Jung authored at least 15 papers between 2010 and 2017.

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Bibliography

2017
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

2014
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.
Commun. ACM, 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012


Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A study of IR-drop noise issues in 3D ICs with through-silicon-vias.
Proceedings of the IEEE International Conference on 3D System Integration, 2010


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