James Laudon

According to our database1, James Laudon authored at least 25 papers between 1987 and 2019.

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Bibliography

2019
GDP: Generalized Device Placement for Dataflow Graphs.
CoRR, 2019

2017
In-Datacenter Performance Analysis of a Tensor Processing Unit.
CoRR, 2017


2009
Throughput-Oriented Multicore Processors.
Proceedings of the Multicore Processors and Systems, 2009

2007
iChip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2007

The Coming Wave of Multithreaded Chip Multiprocessors.
International Journal of Parallel Programming, 2007

Virtual private caches.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Multi-Core Microprocessors Are Here.
;login:, 2006

Fair Queuing Memory Systems.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005
Performance/Watt: the new server focus.
SIGARCH Computer Architecture News, 2005

The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.
SIGARCH Computer Architecture News, 2005

Maximizing CMP Throughput with Mediocre Cores.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

1998
The DASH Prototype: Implementation and Performance.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: The DASH Prototype: Implementation and Performance.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997
The SGI Origin: A ccNUMA Highly Scalable Server.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

System overview of the SGI Origin 200/2000 product line.
Proceedings of the Proceedings IEEE COMPCON 97, 1997

1994
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations.
Proceedings of the ASPLOS-VI Proceedings, 1994

Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors.
Proceedings of the Multithreaded Computer Architecture, 1994

1993
The DASH Prototype: Logic Overhead and Performance.
IEEE Trans. Parallel Distrib. Syst., 1993

1992
The Stanford Dash Multiprocessor.
IEEE Computer, 1992

Architectural and implementation tradeoffs in the design of multiple-context processors.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1990
The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

Design of scalable shared-memory multiprocessors: the DASH approach.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1987
The ZS-1 Central Processor.
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987


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