Maxime Pelcat

According to our database1, Maxime Pelcat authored at least 84 papers between 2008 and 2019.

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Bibliography

2019
Probabilistic Approach Versus Machine Learning for One-Shot Quad-Tree Prediction in an Intra HEVC Encoder.
Signal Processing Systems, 2019

Algorithmic-Level Approximate Computing Applied to Energy Efficient HEVC Decoding.
IEEE Trans. Emerging Topics Comput., 2019

DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping.
Microprocess. Microsystems, 2019

On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion.
J. Real-Time Image Processing, 2019

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
Embedded Systems Letters, 2019

OpenDenoising: an Extensible Benchmark for Building Comparative Studies of Image Denoisers.
CoRR, 2019

Electro-Magnetic Side-Channel Attack Through Learned Denoising and Classification.
CoRR, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

Convex Energy Optimization of Streaming Applications for MPSoCs.
Proceedings of the IEEE International Conference on Acoustics, 2019

Exploiting reconfigurable computing in 5G: a case study of latency critical function: Invited Paper.
Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019

Extending Architecture Modeling for Signal Processing towards GPUs.
Proceedings of the 27th European Signal Processing Conference, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs.
Signal Processing Systems, 2018

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Accelerating CNN inference on FPGAs: A Survey.
CoRR, 2018

Delays and states in dataflow models of computation.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it!
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Machine Learning Based Choice of Characteristics for the One-Shot Determination of the HEVC Intra Coding Tree.
Proceedings of the 2018 Picture Coding Symposium, 2018

A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Energy-Awareness and Performance Management with Parallel Dataflow Applications.
Signal Processing Systems, 2017

Smart search space reduction for approximate computing: A low energy HEVC encoder case study.
J. Syst. Archit., 2017

Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture.
J. Syst. Archit., 2017

Efficient DVFS for low power HEVC software decoder.
J. Real-Time Image Processing, 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
Embedded Systems Letters, 2017

Tactics to Directly Map CNN Graphs on Embedded FPGAs.
Embedded Systems Letters, 2017

Hardware Automated Dataflow Deployment of CNNs.
CoRR, 2017

Prediction of quad-tree partitioning for budgeted energy HEVC encoding.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Exploring the performance of partially reconfigurable point-to-point interconnects.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Adaptive software-augmented hardware reconfiguration with dataflow design automation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Why TanH is a Hardware Friendly Activation Function for CNNs.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

Hardware Acceleration of the Tracking Learning Detection (TLD) Algorithm on FPGA.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

Constrain the Docile CTUs: An In-Frame complexity allocator for HEVC Intra encoders.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Energy reduction opportunities in an HEVC real-time encoder.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Reducing computational complexity in HEVC decoder for mobile energy saving.
Proceedings of the 25th European Signal Processing Conference, 2017

Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cross-layer design of reconfigurable cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

On Learning the Energy Model of an MPSoC for Convex Optimization.
Proceedings of the Computing Frontiers Conference, 2017

2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
Signal Processing Systems, 2016

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies.
Signal Processing Systems, 2016

On Memory Reuse Between Inputs and Outputs of Dataflow Actors.
ACM Trans. Embedded Comput. Syst., 2016

Low power HEVC software decoder for mobile devices.
J. Real-Time Image Processing, 2016

Off-Line DVFS Integration in MDE-Based Design Space Exploration Framework for MP2SoC Systems.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016

Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Distributed Memory Allocation Technique for Synchronous Dataflow Graphs.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Design productivity of a high level synthesis compiler versus HDL.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Energy Efficient Scheduling of Real Time Signal Processing Applications through Combined DVFS and DPM.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Demo GPStudio: a toolchain for FPGA-based Smart Cameras: Demo Paper.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Propagation of Quantification Error Over Convolutional Neural Network layers: PhD Forum.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithms.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Design of multicore HEVC decoders using actor-based dataflow models and OpenMP.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Estimating encoding complexity of a real-time embedded software HEVC codec.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Energy reduction in video systems: the GreenVideo project.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application.
Signal Processing Systems, 2015

Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems.
Proceedings of the Software Engineering, 2015

A DVFS based HEVC decoder for energy-efficient software implementation on embedded processors.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Energy efficiency of a parallel HEVC software decoder for embedded devices.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

A modified HEVC decoder for low power decoding.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Power-aware HEVC decoding with tunable image quality.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Efficient multicore implementation of an advanced generator of discrete chaotic sequences.
Proceedings of the 9th International Conference for Internet Technology and Secured Transactions, 2014

Just-in-time scheduling techniques for multicore signal processing systems.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Energy efficiency and performance management of parallel dataflow applications.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

MARTE to ΠSDF transformation for data-intensive applications analysis.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
Physical Layer Multi-Core Prototyping - A Dataflow-Based Approach for LTE eNodeB
Lecture Notes in Electrical Engineering 171, Springer, ISBN: 978-1-4471-4209-6, 2013

PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Scheduling of parallelized synchronous dataflow actors.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Real-time GPU-based local stereo matching method.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Building a RTOS for MPSoC dataflow programming.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2010
Prototypage Rapide et Génération de Code pour DSP Multi-Coeurs Appliqués à la Couche Physique des Stations de Base 3GPP LTE. (Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs).
PhD thesis, 2010

Adaptive multicore scheduling for the LTE uplink.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
An Open Framework for Rapid Prototyping of Signal Processing Applications.
EURASIP J. Emb. Sys., 2009

Scalable compile-time scheduler for multi-core architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm
CoRR, 2008


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