Maxime Pelcat
Orcid: 0000-0002-1158-0915
According to our database1,
Maxime Pelcat
authored at least 105 papers
between 2008 and 2023.
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Bibliography
2023
Automatic CNN Model Partitioning for GPU/FPGA-based Embedded Heterogeneous Accelerators using Geometric Programming.
J. Signal Process. Syst., October, 2023
Flydeling: Streamlined Performance Models for Hardware Acceleration of CNNs through System Identification.
ACM Trans. Model. Perform. Evaluation Comput. Syst., September, 2023
Proceedings of the Smart Card Research and Advanced Applications, 2023
You Only Get One-Shot: Eavesdropping Input Images to Neural Network by Spying SoC-FPGA Internal Bus.
Proceedings of the 18th International Conference on Availability, Reliability and Security, 2023
2022
SECURE-GEGELATI Always-On Intrusion Detection through GEGELATI Lightweight Tangled Program Graphs.
J. Signal Process. Syst., 2022
Virtual Triggering: a Technique to Segment Cryptographic Processes in Side-Channel Traces.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Ultra-Fast Machine Learning Inference through C Code Generation for Tangled Program Graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Imbalanced classification with tpg genetic programming: impact of problem imbalance and selection mechanisms.
Proceedings of the GECCO '22: Genetic and Evolutionary Computation Conference, Companion Volume, Boston, Massachusetts, USA, July 9, 2022
2021
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021
Des. Autom. Embed. Syst., 2021
CoRR, 2021
CoRR, 2021
PathTracing: Raising the Level of Understanding of Processing Latency in Heterogeneous MPSoCs.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021
Gegelati: Lightweight Artificial Intelligence through Generic and Evolvable Tangled Program Graphs.
Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021
2020
Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure?
IEEE Trans. Netw. Serv. Manag., 2020
Multim. Tools Appl., 2020
Microprocess. Microsystems, 2020
Proceedings of the 22nd IEEE International Workshop on Multimedia Signal Processing, 2020
Opendenoising: An Extensible Benchmark for Building Comparative Studies of Image Denoisers.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
Probabilistic Approach Versus Machine Learning for One-Shot Quad-Tree Prediction in an Intra HEVC Encoder.
J. Signal Process. Syst., 2019
IEEE Trans. Emerg. Top. Comput., 2019
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping.
Microprocess. Microsystems, 2019
On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion.
J. Real Time Image Process., 2019
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
IEEE Embed. Syst. Lett., 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Exploiting reconfigurable computing in 5G: a case study of latency critical function: Invited Paper.
Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019
Proceedings of the 27th European Signal Processing Conference, 2019
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs.
J. Signal Process. Syst., 2018
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Machine Learning Based Choice of Characteristics for the One-Shot Determination of the HEVC Intra Coding Tree.
Proceedings of the 2018 Picture Coding Symposium, 2018
A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
J. Signal Process. Syst., 2017
Smart search space reduction for approximate computing: A low energy HEVC encoder case study.
J. Syst. Archit., 2017
Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture.
J. Syst. Archit., 2017
J. Real Time Image Process., 2017
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
IEEE Embed. Syst. Lett., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Adaptive software-augmented hardware reconfiguration with dataflow design automation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Proceedings of the 25th European Signal Processing Conference, 2017
Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Computing Frontiers Conference, 2017
2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
J. Signal Process. Syst., 2016
Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies.
J. Signal Process. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
J. Real Time Image Process., 2016
Off-Line DVFS Integration in MDE-Based Design Space Exploration Framework for MP2SoC Systems.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016
Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Energy Efficient Scheduling of Real Time Signal Processing Applications through Combined DVFS and DPM.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
Propagation of Quantification Error Over Convolutional Neural Network layers: PhD Forum.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithms.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application.
J. Signal Process. Syst., 2015
Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems.
Proceedings of the Software Engineering, 2015
A DVFS based HEVC decoder for energy-efficient software implementation on embedded processors.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015
Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Efficient multicore implementation of an advanced generator of discrete chaotic sequences.
Proceedings of the 9th International Conference for Internet Technology and Secured Transactions, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Lecture Notes in Electrical Engineering 171, Springer, ISBN: 978-1-4471-4209-6, 2013
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
2010
Prototypage Rapide et Génération de Code pour DSP Multi-Coeurs Appliqués à la Couche Physique des Stations de Base 3GPP LTE. (Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs).
PhD thesis, 2010
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
EURASIP J. Embed. Syst., 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm
CoRR, 2008