Aida Todri

Orcid: 0000-0001-8573-2910

Affiliations:
  • LIRMM Montpellier, France


According to our database1, Aida Todri authored at least 102 papers between 2007 and 2024.

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Bibliography

2024
ClassONN: Classification with Oscillatory Neural Networks Using the Kuramoto Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Operating Coupled VO₂-Based Oscillators for Solving Ising Models.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

A mixed-signal oscillatory neural network for scalable analog computations in phase domain.
Neuromorph. Comput. Eng., September, 2023

How fast can vanadium dioxide neuron-mimicking devices oscillate? Physical mechanisms limiting the frequency of vanadium dioxide oscillators.
Neuromorph. Comput. Eng., September, 2023

Training energy-based single-layer Hopfield and oscillatory networks with unsupervised and supervised algorithms for image classification.
Neural Comput. Appl., September, 2023

Simulation and implementation of two-layer oscillatory neural networks for image edge detection: bidirectional and feedforward architectures.
Neuromorph. Comput. Eng., March, 2023

Enabling Multi-programming Mechanism for Quantum Computing in the NISQ Era.
Quantum, February, 2023

Roadmap for Unconventional Computing with Nanotechnology.
CoRR, 2023

SIFT-ONN: SIFT Feature Detection Algorithm Employing ONNs for Edge Detection.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023

Building Oscillatory Neural Networks: AI Applications and Physical Design Challenges.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Energy-Efficient Machine Learning Acceleration: From Technologies to Circuits and Systems.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural Network.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Two-Layered Oscillatory Neural Networks with Analog Feedforward Majority Gate for Image Edge Detection Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase.
IEEE Trans. Neural Networks Learn. Syst., 2022

Introduction to the Special Issue on Monolithic 3D: Technology, Design and Computing Systems Applications Perspectives.
ACM J. Emerg. Technol. Comput. Syst., 2022

Oscillatory Neural Network as Hetero-Associative Memory for Image Edge Detection.
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022

Oscillatory Neural Network for Edge Computing: A Mobile Robot Obstacle Avoidance Application.
Proceedings of the IEEE International Conference on Metrology for Extended Reality, 2022

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4.
Proceedings of the International Joint Conference on Neural Networks, 2022

On-Chip Learning with a 15-neuron Digital Oscillatory Neural Network Implemented on ZYNQ Processor.
Proceedings of the ICONS 2022: International Conference on Neuromorphic Systems, Knoxville, TN, USA, July 27, 2022

How Parallel Circuit Execution Can Be Useful for NISQ Computing?
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Insights Into the Dynamics of Coupled VO<sub>2</sub> Oscillators for ONNs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Advanced Design Methods From Materials and Devices to Circuits for Brain-Inspired Oscillatory Neural Networks for Edge Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Multi-Scale Modeling and Simulation Flow for Oscillatory Neural Networks for Edge Computing.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Analyzing crosstalk error in the NISQ era.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Oscillatory Neural Networks for Edge AI Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Frequency Injection Locking-Controlled Oscillations for Synchronized Operations in VO2 Crossbar Devices.
Proceedings of the Device Research Conference, 2021

2020
A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era.
CoRR, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications.
Int. J. Circuit Theory Appl., 2019

Energy Autonomous Wearable Sensors for Smart Healthcare: A Review.
CoRR, 2019

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018
A high-reliability and low-power computing-in-memory implementation within STT-MRAM.
Microelectron. J., 2018

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.
J. Comput. Sci. Technol., 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018


2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
A Study of 3-D Power Delivery Networks With Multiple Clock Domains.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliab., 2016

Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era.
ACM J. Emerg. Technol. Comput. Syst., 2016

Investigation of electrical and thermal properties of carbon nanotube interconnects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Physical description and analysis of doped carbon nanotube interconnects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Quantitative evaluation of reliability and performance for STT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies.
ACM J. Emerg. Technol. Comput. Syst., 2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

On Analysis of On-chip DC-DC Converters for Power Delivery Networks.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Globally Constrained Locally Optimized 3-D Power Delivery Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

TSV aware timing analysis and diagnosis in paths with multiple TSVs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A Comprehensive Evaluation of Functional Programs for Power-Aware Test.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

iBoX - Jitter based Power Supply Noise sensor.
Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Test and diagnosis of power switches.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Timing-aware ATPG for critical paths with multiple TSVs.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An intra-cell defect grading tool.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Design Space Exploration Of Emerging Technologies For Energy Efficiency.
, 2014

2013
A Study of Tapered 3-D TSVs for Power and Thermal Integrity.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A built-in scheme for testing and repairing voltage regulators of low-power srams.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013

A novel method to mitigate TSV electromigration for 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Effect-cause intra-cell diagnosis at transistor level.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013

Computing detection probability of delay defects in signal line tsvs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Test solution for data retention faults in low-power SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A pseudo-dynamic comparator for error detection in fault tolerant architectures.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-power SRAMs power mode control logic: Failure analysis and test solutions.
Proceedings of the 2012 IEEE International Test Conference, 2012

Evaluation of test algorithms stress effect on SRAMs under neutron radiation.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Defect analysis in power mode control logic of low-power SRAMs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Through-Silicon-Via resistive-open defect analysis.
Proceedings of the 17th IEEE European Test Symposium, 2012

Coupling-based resistive-open defects in TAS-MRAM architectures.
Proceedings of the 17th IEEE European Test Symposium, 2012

Impact of resistive-open defects on the heat current of TAS-MRAM architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power Supply Noise Sensor Based on Timing Uncertainty Measurements.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Why and How Controlling Power Consumption during Test: A Survey.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Power Delivery for Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reliability Analysis and Optimization of Power-Gated ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Failure Analysis and Test Solutions for Low-Power SRAMs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009
A study of decoupling capacitor effectiveness in power and ground grid networks.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Electromigration study of power-gated grids.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
A study of reliability issues in clock distribution networks.
Proceedings of the 26th International Conference on Computer Design, 2008

Power supply noise aware workload assignment for multi-core systems.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Electromigration and voltage drop aware power grid optimization for power gated ICs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Analysis and optimization of power-gated ICs with multiple power gating configurations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007


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