Jung-Woo Sull

According to our database, Jung-Woo Sull authored at least 6 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS.

Jung-Woo Sull, Minkyo Shim, Jung-Hun Park, Sanghee Lee, Deog-Kyoon Jeong

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS.

Jung-Woo Sull, Soyeong Shin, Jonghyun Oh, Kwang-Hoon Lee, Jihee Kim, Jung-Hun Park, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller.

Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop.

Chang-Soo Yoon, Han-Gon Ko, Byung-Jun Kang, Jung-Woo Sull, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS.

Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS.

Jung-Woo Sull, Hyungrok Do, Deog-Kyoon Jeong

Proceedings of the International SoC Design Conference, 2020