Hyungrok Do

According to our database1, Hyungrok Do authored at least 11 papers between 2018 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Outer-Points shaver: Robust graph-based clustering via node cutting.
Pattern Recognit., 2020

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.
IEEE J. Solid State Circuits, 2020

Graph Structured Sparse Subset Selection.
Inf. Sci., 2020

Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Visualization of streamline tracing inlet-isolator flows using a planar laser Rayleigh scattering imaging technique.
J. Vis., 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Clear the Fog: Combat Value Assessment in Incomplete Information Games with Convolutional Encoder-Decoders.
CoRR, 2018

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018