Chan-Ho Kye

According to our database, Chan-Ho Kye authored at least 5 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2023

A 0.000261 mm² Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS.

Chan-Ho Kye, Kyojin Choo

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2020

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.

Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, Deog-Kyoon Jeong

IEEE Trans. Very Large Scale Integr. Syst., 2020

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.

Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

A 370-fJ/b, 0.0056 mm²/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.

Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm² Controller and 80ns Recovery Time.

Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong

Proceedings of the IEEE International Solid- State Circuits Conference, 2019