Jyotishman Saikia
According to our database1,
Jyotishman Saikia
authored at least 11 papers
between 2017 and 2024.
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Bibliography
2024
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks.
IEEE J. Solid State Circuits, June, 2024
2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017