Shreyas K. Venkataramanaiah
According to our database1,
Shreyas K. Venkataramanaiah
authored at least 15 papers
between 2017 and 2023.
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Bibliography
2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Neuromorph. Comput. Eng., December, 2022
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
CoRR, 2019
FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning.
Proceedings of Machine Learning and Systems 2019, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2017
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017