Injune Yeo

Orcid: 0000-0002-4596-6170

According to our database1, Injune Yeo authored at least 16 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023

Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 92 F<sup>2</sup> / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference.
IEEE Micro, 2022

Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A Hardware and Energy-Efficient Online Learning Neural Network With an RRAM Crossbar Array and Stochastic Neurons.
IEEE Trans. Ind. Electron., 2021

2019
A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array.
IEEE Trans. Biomed. Circuits Syst., 2019

A CMOS-based Resistive Crossbar Array with Pulsed Neural Network for Deep Learning Accelerator.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Implementation of STDP Learning for Non-volatile Memory-based Spiking Neural Network using Comparator Metastability.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2016
Stochastic implementation of the activation function for artificial neural networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016


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