Ahmed Elkholy

According to our database1, Ahmed Elkholy authored at least 39 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques.
IEEE J. Solid State Circuits, 2020

Arabian horse identification based on whale optimised multi-class support vector machine.
Int. J. Comput. Appl. Technol., 2020

2019
A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection.
IEEE J. Solid State Circuits, 2019

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers.
IEEE J. Solid State Circuits, 2019

A 15-Gb/s Sub-Baud-Rate Digital CDR.
IEEE J. Solid State Circuits, 2019

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.
IEEE J. Solid State Circuits, 2019

A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.
IEEE J. Solid State Circuits, 2018

A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier.
IEEE J. Solid State Circuits, 2018

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits, 2017

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
IEEE J. Solid State Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


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