# Romesh Kumar Nandwana

According to our database

Collaborative distances:

^{1}, Romesh Kumar Nandwana authored at least 22 papers between 2013 and 2019.Collaborative distances:

## Timeline

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#### On csauthors.net:

## Bibliography

2019

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links.

IEEE J. Solid State Circuits, 2019

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.

IEEE J. Solid State Circuits, 2019

2017

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.

IEEE J. Solid State Circuits, 2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.

IEEE J. Solid State Circuits, 2017

IEEE J. Solid State Circuits, 2017

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.

IEEE J. Solid State Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.

IEEE J. Solid State Circuits, 2015

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator.

IEEE J. Solid State Circuits, 2015

Proceedings of the Symposium on VLSI Circuits, 2015

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS.

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

IEEE J. Solid State Circuits, 2014

Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter.

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013