Romesh Kumar Nandwana

According to our database, Romesh Kumar Nandwana authored at least 22 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links.

Kadaba Lakshmikumar, Alexander Kurylak, Manohar Nagaraju, Richard Booth, Romesh Kumar Nandwana, Joe Pampanin, Vito Boccuzzi

IEEE J. Solid State Circuits, 2019

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.

Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2019

2017

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.

Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.0021 mm² 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.

Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2017

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2017

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.

Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.

Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.

Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.

Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.

Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.

Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2015

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator.

Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu

Proceedings of the Symposium on VLSI Circuits, 2015

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm² 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS.

Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.

Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis.

Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2014

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.

Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu

Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter.

Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013