Prabhakar Kudva

Orcid: 0000-0003-0854-8612

According to our database1, Prabhakar Kudva authored at least 46 papers between 1974 and 2023.

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Bibliography

2023
A Scalable Space-efficient In-database Interpretability Framework for Embedding-based Semantic SQL Queries.
CoRR, 2023

2021
Cryptomining Detection in Container Clouds Using System Calls and Explainable Machine Learning.
IEEE Trans. Parallel Distributed Syst., 2021

Learning Without Forgetting: A New Framework for Network Cyber Security Threat Detection.
IEEE Access, 2021

2020
Dynamically Generated Compact Neural Networks for Task Progressive Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Dynamic Autoselection and Autotuning of Machine Learning Models for Cloud Network Analytics.
IEEE Trans. Parallel Distributed Syst., 2019

Criteria for Learning without Forgetting in Artificial Neural Networks.
Proceedings of the 2019 IEEE International Conference on Cognitive Computing, 2019

Generation of Stressmarks for Early Stage Soft-Error Modeling.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

2018
Security Analysis of Container Images Using Cloud Analytics Framework.
Proceedings of the Web Services - ICWS 2018, 2018

Exploring Serverless Computing for Neural Network Training.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2014
Automated detection and verification of parity-protected memory elements.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers.
IEEE Trans. Computers, 2013

Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2011
Error Tolerance in Server Class Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Exponent monitoring for low-cost concurrent error detection in FPU control logic.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Reliability Challenges and System Performance at the Architecture Level.
IEEE Des. Test Comput., 2009

2008
Soft-error resilience of the IBM POWER6 processor.
IBM J. Res. Dev., 2008

Phaser: Phased methodology for modeling the system-level effects of soft errors.
IBM J. Res. Dev., 2008

Soft-error resilience of the IBM POWER6 processor input/output subsystem.
IBM J. Res. Dev., 2008

Statistical Fault Injection.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2006
Rethinking Processor Design: Parameter Correlations.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
Implicit enumeration of structural changes in circuit optimization.
Proceedings of the 41th Design Automation Conference, 2004

2003
Measurements for structural logic synthesis optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Understanding metrics in logic synthesis for routability enhancement.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Physical synthesis methodology for high performance microprocessors.
Proceedings of the 40th Design Automation Conference, 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Metrics for structural logic synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Synchronous Interlocked Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

Combinatorial cell design for CMOS libraries.
Integr., 2000

Transformational Placement and Synthesis.
Proceedings of the 2000 Design, 2000

High-Level Asynchronous System Design Using the ACK Framework.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Peephole optimization of asynchronous macromodule networks.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Performance Driven Optimization of Network Length in Physical Placement.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Gate-size selection for standard cell libraries.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Asynchronous Transpose-Matrix Architectures.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.
Proceedings of the 33st Conference on Design Automation, 1996

A Technique for Synthesizing Distributed Burst-mode Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1994
Testing two-phase transition signaling based self-timed circuits in a synthesis environment.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Performance Analysis and Optimization of Asynchronous Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A technique for estimating power in asynchronous circuits.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1992
Load-adaptive control of a single-link flexible manipulator.
IEEE Trans. Syst. Man Cybern., 1992

Towards a Verification Technique for Large Synchronous Circuits.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1974
Stable Adaptive Schemes for System Identification and Control - Part II.
IEEE Trans. Syst. Man Cybern., 1974

Stable Adaptive Schemes for System Identification and Control-Part I.
IEEE Trans. Syst. Man Cybern., 1974


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