Paul G. Villarrubia

According to our database1, Paul G. Villarrubia authored at least 29 papers between 1997 and 2011.

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Bibliography

2011
Robust partitioning for hardware-accelerated functional verification.
Proceedings of the 48th Design Automation Conference, 2011

2008
Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast interconnect synthesis with layer assignment.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Challenges at 45nm and beyond.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

The coming of age of physical synthesis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Electrical Correction Using Resizing and Buffering.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

ISPD 2005/2006 Placement Benchmarks.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On whitespace and stability in physical synthesis.
Integr., 2006

2005
Physical design tools for hierarchy.
Proceedings of the 2005 International Symposium on Physical Design, 2005

The ISPD2005 placement contest and benchmark suite.
Proceedings of the 2005 International Symposium on Physical Design, 2005

A semi-persistent clustering technique for VLSI circuit placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Diffusion-based placement migration.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Benchmarking for large-scale placement and beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

True crosstalk aware incremental placement with noise map.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Effective free space management for cut-based placement via analytical constraint generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A practical methodology for early buffer and wire resource allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Important placement considerations for modern VLSI chips.
Proceedings of the 2003 International Symposium on Physical Design, 2003

On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Free space management for cut-based placement.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

2000
Transformational Placement and Synthesis.
Proceedings of the 2000 Design, 2000

"Timing closure by design, " a high frequency microprocessor design methodology.
Proceedings of the 37th Conference on Design Automation, 2000

1997
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997


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