Nozomu Matsuzaki

According to our database, Nozomu Matsuzaki authored at least 4 papers between 1996 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.

Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

IEEE J. Solid State Circuits, 2010

2007

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current.

Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory.

Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1996

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

IEEE J. Solid State Circuits, 1996