Kazuei Hironaka

According to our database, Kazuei Hironaka authored at least 24 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Power Analysis and Power Modeling of Directly-Connected FPGA Clusters.

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano

IEICE Trans. Inf. Syst., December, 2023

A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.

M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

IEICE Trans. Inf. Syst., November, 2023

2022

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System.

Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano

IEICE Trans. Inf. Syst., December, 2022

A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems.

Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Power Analysis of Directly-connected FPGA Clusters.

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.

Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2021

Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).

Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano

IEICE Trans. Inf. Syst., 2021

M-KUBOS/PYNQ Cluster for multi-access edge computing.

Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.

Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

Implementing VTA, a tensor accelerator on Flow-in-Cloud.

Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020

A Method of Partitioning Convolutional Layer to Multiple FPGAs.

Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano

Proceedings of the International SoC Design Conference, 2020

Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.

Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.

Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019

Multi-FPGA Management on Flow-in-Cloud Prototype System.

Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano

Proceedings of the 20th IEEE/ACIS International Conference on Software Engineering, 2019

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System.

Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW.

Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Demonstration of Flow-in-Cloud: A Multi-FPGA System.

Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study.

Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2012

Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array.

Toru Katagiri, Kazuei Hironaka, Hideharu Amano

Proceedings of the 15th International Conference on Network-Based Information Systems, 2012

2011

Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.

Kazuei Hironaka, Hideharu Amano

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.

Masayuki Kimura, Kazuei Hironaka, Hideharu Amano

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.

Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Dynamic V_DD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.

Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.

Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Proceedings of the International Conference on Field-Programmable Technology, 2010