Yoshihiro Yasuda

According to our database, Yoshihiro Yasuda authored at least 6 papers between 2009 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

CMA-2 : The second prototype of a low power reconfigurable accelerator.

Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.

Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo

IEEE Micro, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.

Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.

Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Proceedings of the International Conference on Field-Programmable Technology, 2010

MuCCRA-3: a low power dynamically reconfigurable processor array.

Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.

Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009