Akira Yamamoto
According to our database1,
Akira Yamamoto
authored at least 26 papers
between 1983 and 2022.
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Bibliography
2022
A Highly Backdrivable Robotic Arm using Low Friction and High Accuracy Cycloidal Geared Motors: ALFHA.
Proceedings of the IEEE/SICE International Symposium on System Integration, 2022
2021
A Closed Queueing Network Model for SSD Write Performance Analysis Utilizing the Batch Processing Method.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021
2015
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
2014
Proceedings of the IEEE 38th Annual Computer Software and Applications Conference, 2014
2013
A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage.
IEEE J. Solid State Circuits, 2013
Using a High-Speed Movie Camera to Evaluate Slice Dropping in Clinical Image Interpretation with Stack Mode Viewers.
J. Digit. Imaging, 2013
A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
Development of Flowering Stage Inspection Equipment for Small-Flowered Chrysanthemum.
J. Robotics Mechatronics, 2011
2009
A 14.6<sup>th</sup>-order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2004
Proceedings of the Medical Imaging 2004: Image Processing, 2004
A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
Automated volume measurements of pulmonary emphysema on 3D chest CT images.
Proceedings of the CARS 2003. Computer Assisted Radiology and Surgery. Proceedings of the 17th International Congress and Exhibition, 2003
2002
IEEE J. Solid State Circuits, 2002
2000
Queuing model with interrupt enable points and its application to the analyses of suspend controls of disk units.
Syst. Comput. Jpn., 2000
1999
Specification of Real-Time Systems Using a Timed Automata Model with Shared Variables and Verification of Partial-Deadlock Freeness.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999
1995
IEICE Trans. Inf. Syst., 1995
1986
New Gener. Comput., 1986
Evaluation of PSI Micro-Interpreter.
Proceedings of the Spring COMPCON'86, 1986
1985
Proceedings of the Logic Programming '85, 1985
1984
A Microprogrammed Interpreter for the Personal Sequential Inference Machine.
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984
Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984
1983
New Gener. Comput., 1983
The Personal Sequential Inference Machine (PSI): Its Design and Machine Architecture.
Proceedings of the Logic Programming Workshop '83, Praia da Falésia, Algarve, Portugal, 26 June, 1983