Kenneth Reyer

According to our database, Kenneth Reyer authored at least 4 papers between 2000 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology.

N. Jungmann, R. Joshi, E. Kachir, K. Shimanovich, B. He, T. Cohen, T. Miller, D. Leu, Dinesh Kannambadi, I. Wagner, Kenneth Reyer, H. Konen, M. Suleiman, V. Sindhe, Y. Freiman

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2016

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2016

2015

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2000

Design validation of .18 μm 1 GHz cache and register arrays.

Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000