Thomas J. Knips

According to our database, Thomas J. Knips authored at least 5 papers between 2000 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2016

2015

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.

John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2006

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.

John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2000

Design validation of .18 μm 1 GHz cache and register arrays.

Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000