Kimish Patel

According to our database1, Kimish Patel authored at least 18 papers between 2004 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
NFRA: Generalized Network Flow-Based Resource Allocation for Hosting Centers.
IEEE Trans. Computers, 2013

2009
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
GOP-Level Dynamic Thermal Management in MPEG-2 Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2008

In-order pulsed charge recycling in off-chip data buses.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Minimizing power dissipation during write operation to register files.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Active bank switching for temperature control of the register file in a microprocessor.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.
J. Low Power Electron., 2006

Dynamic thermal management for MPEG-2 decoding.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

STV-Cache: a leakage energy-efficient architecture for data caches.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

B<sup>2</sup>Sim: : a fast micro-architecture simulator based on basic block characterization.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Optimised Mapping of the QSDPCM Video Codec on MPARM: Shared Bus is not the Bottleneck.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Frame Buffer Energy Optimization by Pixel Prediction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Zero clustering: an approach to extend zero compression to instruction caches.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Reducing cache misses by application-specific re-configurable indexing.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.
Proceedings of the 2004 Design, 2004

Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip.
Proceedings of the Ultra Low-Power Electronics and Design, 2004


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