Naveen Suda

According to our database¹, Naveen Suda authored at least 24 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Links

On csauthors.net:

Bibliography

2024

Towards Open-World Gesture Recognition.

[BibT_eX]

[DOI]

CoRR, 2024

2022

Collapsible Linear Blocks for Super-Efficient Super Resolution.

[BibT_eX]

[DOI]

Proceedings of Machine Learning and Systems 2022, 2022

2021

EdgeAl: A Vision for Deep Learning in the IoT Era.

[BibT_eX]

[DOI]

Kartikeya Bhardwaj

Naveen Suda

Radu Marculescu

IEEE Des. Test, 2021

2019

EdgeAI: A Vision for Deep Learning in IoT Era.

[BibT_eX]

[DOI]

Kartikeya Bhardwaj

Naveen Suda

Radu Marculescu

CoRR, 2019

Dream Distillation: A Data-Independent Model Compression Framework.

[BibT_eX]

[DOI]

Kartikeya Bhardwaj

Naveen Suda

Radu Marculescu

CoRR, 2019

SenseHAR: a robust virtual activity sensor for smartphones and wearables.

[BibT_eX]

[DOI]

Jeya Vikranth Jeyakumar

Liangzhen Lai

Naveen Suda

Mani B. Srivastava

Proceedings of the 17th Conference on Embedded Networked Sensor Systems, 2019

2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.

[BibT_eX]

[DOI]

Integr., 2018

Rethinking Machine Learning Development and Deployment for Edge Devices.

[BibT_eX]

[DOI]

Liangzhen Lai

Naveen Suda

CoRR, 2018

Federated Learning with Non-IID Data.

[BibT_eX]

[DOI]

CoRR, 2018

CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs.

[BibT_eX]

[DOI]

Liangzhen Lai

Naveen Suda

Vikas Chandra

CoRR, 2018

Not All Ops Are Created Equal!

[BibT_eX]

[DOI]

Liangzhen Lai

Naveen Suda

Vikas Chandra

CoRR, 2018

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Enabling deep learning at the IoT edge.

[BibT_eX]

[DOI]

Liangzhen Lai

Naveen Suda

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2017

Hello Edge: Keyword Spotting on Microcontrollers.

[BibT_eX]

[DOI]

CoRR, 2017

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control.

[BibT_eX]

[DOI]

CoRR, 2017

Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations.

[BibT_eX]

[DOI]

Liangzhen Lai

Naveen Suda

Vikas Chandra

CoRR, 2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

High-performance face detection with CPU-FPGA acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2013

Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Naveen Suda

Timeline

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On csauthors.net:

Bibliography

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