Zoltán Endre Rákossy

Orcid: 0000-0001-5724-9569

Affiliations:
  • RWTH Aachen University, Germany


According to our database1, Zoltán Endre Rákossy authored at least 18 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Design and synthesis of reconfigurable control-flow structures for CGRA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Modeling, analysis and exploration of layers: A 3D computing architecture.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array.
Proceedings of the Design, Automation and Test in Europe, 2013

CoARX: a coprocessor for ARX-based cryptographic algorithms.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.
Int. J. Reconfigurable Comput., 2012

ASIC synthesis using Architecture Description Language.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Design and analysis of layered coarse-grained reconfigurable architecture.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011
Combinational logic synthesis for material implication.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2009
Hot-Swapping architecture extension for mitigation of permanent functional unit faults.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embed. Comput. Syst., 2008

2007
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007


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