Konrad Lai

According to our database1, Konrad Lai authored at least 26 papers between 1981 and 2016.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
RowHammer: Reliability Analysis and Security Implications.
CoRR, 2016

2014
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing.
Proceedings of the International Conference for High Performance Computing, 2013

2006
Scalable Load and Store Processing in Latency-Tolerant Processors.
IEEE Micro, 2006

2005
Better Branch Prediction Through Prophet/Critic Hybrids.
IEEE Micro, 2005

Virtualizing Transactional Memory.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Scalable Load and Store Processing in Latency Tolerant Processors.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

The Impact of Performance Asymmetry in Emerging Multicore Architectures.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
A New Address-Free Memory Hierarchy Layer for Zero-Cycle Load.
J. Instruction-Level Parallelism, 2004

Prophet/Critic Hybrid Branch Prediction.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

A Minimal Dual-Core Speculative Multi-Threading Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Signature Buffer: Bridging Performance Gap between Registers and Caches.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003
Address-free memory access based on program syntax correlation of loads and stores.
IEEE Trans. VLSI Syst., 2003

Recycling waste: exploiting wrong-path execution to improve branch prediction.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Implementation of HW$im - A Real-Time Configurable Cache Simulator.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Dynamic addressing memory arrays with physical locality.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Bloom filtering cache misses for accurate data speculation and prefetching.
Proceedings of the 16th international conference on Supercomputing, 2002

2001
Direct load: dependence-linked dataflow resolution of load address and cache coordinate.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1992
Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1990
A VLSI-intensive fault-tolerant computer architecture.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1983
Interprocess Communication and Processor Dispatching on the Intel 432
ACM Trans. Comput. Syst., 1983

1982
Supporting Ada Memory Management in the iAPX-432.
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982

1981
A Unified Model and Implementation for Interprocess Communication in a Multiprocessor Environment.
Proceedings of the Eighth Symposium on Operating System Principles, 1981


  Loading...